(1) Field of the Invention
The present invention relates to integrated circuits on semiconductor substrates, and more particularly to a method for making reliable buried contacts to semiconductor devices without trenches, and further having low sheet resistance between the buried contacts and the semiconductor devices. This is particularly applicable to static random access memory (SRAM) for reducing the design rules for achieving high-density memories with better circuit performance.
(2) Description of the Prior Art
Buried contacts between patterned polysilicon layers and the substrate are used extensively in the semiconductor industry to provide electrical connections, and therefore eliminate the need to form metal links to form the contacts. Buried contacts provide an additional level of local interconnections, thereby freeing up the metal levels for providing global interconnections.
The method of making conventional buried contacts and the problems associated with making these contacts are best understood with reference to FIGS. 1 through 6B of the prior art. FIG. 1 shows a portion of a semiconductor substrate 10 on and in which is formed a field oxide (FOX) 12, surrounding and electrically isolating active device areas. A buried contact and FET are formed next by forming a gate oxide 14 and by depositing a thin polysilicon layer 16. A first photoresist mask 18 is patterned to form the opening for the buried contact. The thin polysilicon layer 16 and gate oxide 14 are etched to form the opening 2, as shown in FIG. 2. A boron (B.sup.11) implant 20 forms an anti-punchthrough (APT) region, and then an N.sup.+ implant, such as phosphorus (p.sup.31), is used to form a buried contact area 22 in the substrate 10, as shown in FIG. 3.
Now as shown in FIG. 4, an N.sup.+ doped second polysilicon/silicide (polycide) layer 24 is deposited over the buried contact areas 22 and over the gate oxide 14 in the active device areas. A patterned second photoresist mask 26, as shown in FIG. 5A, is used to pattern the polycide layer 24 to form the FET gate electrode 24' and concurrently the interconnection 24" to the buried contact 22, as shown in FIG. 5B. If the photoresist pattern is misaligned to the left over the buried contact 22, then the etching of layer 24 can result in an undesirable trench 4 in the substrate, as shown in FIG. 5B. This trench can result in excessive leakage current between the buried contact and the substrate, and/or cause an electrical open between the buried contact 22 and the source/drain contact of the FET having the gate electrode 24' which degrades circuit performance. Now as shown in FIG. 6A, if the second photoresist mask is misaligned to the right, then the source/drain implant 28 for the FET that is done later can be prevented from contacting the buried contact 22 resulting (FIG. 6B) in an undoped (open) area 6 causing high resistance and device degradation, as shown in FIG. 6B.
Several methods have been reported to improve the buried contact structure. One method of forming damage-free buried contacts in the semiconductor substrate without trenches and pitted areas is described by Liu, U.S. Pat. No. 5,550,085, in which a titanium nitride (TiN) or titanium tungsten (TiW) material is deposited over the buried contacts, and then a polysilicon layer is deposited and patterned using the TiN or TiW as an etch-stop layer when etching the polysilicon layer, thereby avoiding trenching. However, Liu's method requires an additional critical etch step to remove the TiN or TiW layer.
Another method for forming self-aligned low-resistance buried contacts is described by Manning, U.S. Pat. No. 5,292,676, in which the patterned photoresist mask used to etch the buried contact openings is de-scummed or cut back to expose a thin first polysilicon layer with a gate oxide thereunder at the periphery of the buried contact openings. Manning then implants the buried contacts, which also are implanted through the peripheral gate oxide areas. This allows the buried contacts with lower resistance to be made to remote N.sup.+ source or drain structures, thereby minimizing the possibility of forming parasitic MOS devices.
Therefore, there is still a strong need in the semiconductor industry to further improve the buried contacts that are both free of trenches and that also provide low resistance between the buried contacts and the source or drain areas of FETs, while allowing tighter ground rule tolerances for making higher density integrated circuits.